CAT34TS02
http://onsemi.com
3
Table 5. A.C. CHARACTERISTICS (V
CC
= 3.3 V ?10%, T
A
= 20癈 to +125癈) (Note 4)
Symbol
Parameter
Min
Max
Units
F
SCL
(Note 5)
Clock Frequency
10
400
kHz
t
HIGH
High Period of SCL Clock
600
ns
t
LOW
Low Period of SCL Clock
1300
ns
t
TIMEOUT
(Note 5)
SMBus SCL Clock Low Timeout
25
35
ms
t
R
(Note 6)
SDA and SCL Rise Time
300
ns
t
F
(Note 6)
SDA and SCL Fall Time
300
ns
t
SU:DAT
(Note 7)
Data Setup Time
100
ns
t
SU:STA
START Condition Setup Time
600
ns
t
HD:STA
START Condition Hold Time
600
ns
t
SU:STO
STOP Condition Setup Time
600
ns
t
BUF
Bus Free Time Between STOP and START
1300
ns
t
HD:DAT
Input Data Hold Time
0
ns
t
DH
(Note 6)
Output Data Hold Time
200
900
ns
T
i
Noise Pulse Filtered at SCL and SDA Inputs
100
ns
t
WR
Write Cycle Time
5
ms
t
PU
(Note 8)
Powerup Delay to Valid Temperature Recording
100
ms
4. Timing reference points are set at 30%, respectively 70% of V
CC
, as illustrated in Figure 23. Bus loading must be such as to allow meeting
the V
IL
, V
OL
as well as the various timing limits.
5. For the CAT34TS02 Rev. B, the TS interface will reset itself and will release the SDA line if the SCL line stays low beyond the t
TIMEOUT
limit.
The timeout countdown is activated in the interval between START and STOP when SCL is low and is reset while SCL is high. The minimum
clock frequency of 10 kHz is an SMBus recommendation; the minimum operating clock frequency for the CAT34TS02s SPD component
is DC, while the minimum operating frequency for the TS component is limited only by the SMBus timeout. For the CAT34TS02 Rev. C,
both the TS and the SPD implement the timeout feature.
6. In a WiredOR system (such as I
2
C or SMBus), SDA rise time is determined by bus loading. Since each bus pulldown device must be
able to sink the (external) bus pullup current (in order to meet the V
IL
and/or V
OL
limits), it follows that SDA fall time is inherently faster than
SDA rise time. SDA rise time can exceed the standard recommended t
R
limit, as long as it does not exceed t
LOW
t
DH
t
SU:DAT
, where t
LOW
and t
DH
are actual values (rather than spec limits). A shorter t
DH
leaves more room for a longer SDA t
R
, allowing for a more capacitive bus
or a larger bus pullup resistor. At the minimum t
LOW
spec limit of 1300 ns, the maximum t
DH
of 900 ns demands a maximum SDA t
R
of 300 ns.
The CAT34TS02s maximum t
DH
is <700 ns, thus allowing for an SDA t
R
of up to 500 ns at minimum t
LOW
.
7. The minimum t
SU:DAT
of 100 ns is a limit recommended by standards. The CAT34TS02 will accept a t
SU:DAT
of 0 ns.
8. The first valid temperature recording can be expected after t
PU
at nominal supply voltage.
Table 6. PIN CAPACITANCE (T
A
= 25癈, V
CC
= 3.3 V, f = 1 MHz)
Symbol
Parameter
Test Conditions/Comments
Min
Max
Unit
C
IN
SDA, EVENT
Pin Capacitance
V
IN
= 0
8
pF
Input Capacitance (other pins)
V
IN
= 0
6
pF
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